1. Field of the Disclosure
The present disclosure relates to a semiconductor integrated circuit device equipped with an output terminal for use for a signal, and more particularly to a semiconductor integrated circuit device that can protect an internal circuit even if a voltage lower than the ground is applied to the output terminal.
2. Description of the Related Art
An integrated circuit (IC) having a sensing function is generally equipped with power supply terminals (+ terminal and − terminal) used to supply electric power from the outside and with an output terminal used to output a sensing signal. If a senor module is installed at a place distant from a controller, these terminals are usually connected to the controller through a cable. Therefore, a power supply line may be connected to the signal output terminal of the IC by mistake due to a miss in cable wiring or the like. In this case, an excessive current may flow into the interior of the IC.
FIG. 4 illustrates a general open drain type of signal output circuit. The signal output circuit illustrated in FIG. 4 is comprised of an N-type MOS transistor 51. With the MOS transistor 51, a source is connected to a ground terminal T1, a drain is connected to an output terminal T2, and a gate accepts a signal IN_B. This output terminal T2 is connected to an external power supply voltage 53 through a pull-up resistor 52. If the MOS transistor 51 is turned off, a voltage VOUT at the output terminal T2 is at a high level; if the MOS transistor 51 is turned on, the voltage VOUT at the output terminal T2 is at a low level. In general, since the output terminal T2 is connected to the external power supply voltage 53 through the pull-up resistor 52, the voltage VOUT at the output terminal T2 will not fall below a ground potential VSS. If there is an erroneous cable connection or the like, however, there may be a case in which the voltage VOUT falls below the ground potential VSS.
FIG. 5 illustrates a case in which, in the signal output circuit illustrated in FIG. 4, the voltage VOUT at the output terminal T2 falls below the ground potential VSS. In the example in FIG. 5, a signal line, which should be connected to the output terminal T2, is connected to the ground terminal T1, and a power supply line on a low voltage side, which should be connected to the ground terminal T1, is connected to the output terminal T2. In this case, a current flows from the ground terminal T1 through a parasitic diode of the MOS transistor 51 to the output terminal T2, as indicated by the dash-dot line.
FIGS. 6A and 6B are drawings to explain a parasitic diode of an N-type MOS transistor 51. FIG. 6A illustrates the structure of the MOS transistor 51, and FIG. 6B illustrates a current flowing into the parasitic diode. When potentials at the source S and bulk B become higher than a potential at the drain D, the parasitic diode present between the bulk (P-well) and the drain of the N-type MOS transistor 51 is brought into conduction, so a current flows as indicated by the dash-dot line in the drawing. When a current flows into the parasitic diode, the circuit becomes unstable and an electric power loss occurs in the parasitic diode.
A possible method used to prevent a current from flowing into a parasitic diode of a MOS transistor is to, for example, insert a diode in the opposite direction from the parasitic diode into a current path separately. However, another problem arises in that a voltage drop or an electric power loss occurs in the diode in a normal operation state. In view of this, Japanese Unexamined Patent Application Publication No. 2000-58756 proposes a method in which an N-type MOS transistor for use for reverse current prevention is provided in series with an N-type MOS transistor for use for signal output.
FIG. 7 illustrates a conventional protection circuit described in Japanese Unexamined Patent Application Publication No. 2000-58756 above. In this protection circuit, a double-diffused metal-oxide-semiconductor (DMOS) transistor MP is provided in series with an N-type DMOS MI for use for signal output.
If an output voltage VOUT is higher than the ground potential VSS, an output signal from a comparator 63 is at the high level. When a high-level signal IN_B is input to the gate of the DMOS transistor MI, the DMOS transistor MI is turned on. When the signal IN_B goes high, an output from an AND circuit 64 goes high and a current flows from a current source 61 into a resistor 62, so the gate of the DMOS transistor MP goes high and the DMOS transistor MP is also turned on. Accordingly, the DMOS transistors MI and MP are both turned on and the output voltage VOUT goes low. Since the channel of the DMOS transistor MP is brought into conduction, a current does not flow into the parasitic diode of the DMOS transistor MP, so an electric power loss does not occur in the parasitic diode.
By contrast, if the output voltage VOUT falls below the ground potential VSS due to an erroneous connection or the like, the output from the comparator 63 goes low and the output from the AND circuit 64 is kept at the low level, so a current does not flow from a current source 61 into the resistor 62. Therefore, the DMOS transistor MP is held in an off state. The parasitic diode of the DMOS transistor MI is in the forward direction with respect to the current flowing from the ground potential VSS to the output terminal. Since the parasitic diode of the DMOS transistor MP is in the opposite direction, however, a reverse current does not flow from the ground terminal to the output terminal.
As described above, the protection circuit illustrated in FIG. 7 can prevent a reverse current due to an erroneous connection or the like. However, if the output terminal is pulled up to a voltage almost equal to a power supply voltage VCC during a normal operation in which there is no erroneous connection, the output voltage VOUT approaches the power supply voltage VCC in a state in which the DMOS transistor MI is turned off and the gate-source voltage of the DMOS transistor MP becomes almost zero, so the DMOS transistor MP is turned off. In this case, when the DMOS transistor MI changes from off to on, a forward current flows into the parasitic diode of the DMOS transistor MP, so an unnecessary electric power loss occurs in the parasitic diode. If the temperature of the IC chip is raised due to heat generated in the parasitic diode, characteristic deterioration and other problems are caused.